Power Optimization at Nanoscale Using Finfets and Its Comparison with Cmos

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors face many limitations such as Short Channel Effects (SCEs), Drain Induced Barrier Lowering (DIBL) and subthreshold leakage. Multigated MOS devices prove to be a better solution to these problems. Thus FinFET device along with various power optimization techniques using FinFETs is described. At the end a comparison of the simulation results at 45nm based on the factors of leakage current, leakage power and delay is given. These results show that FinFET gives better power optimization than MOS transistor at nanoscale.